Mtech Final year Projects

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M.Tech students can get new projects of software, hardware, MATLAB and simulation. Get your final year project idea and tutorial from one of the top M.tech Projects in Software Java Projects, Software DotNet Projects, Software Android Projects, Hardware Embedded Projects, Hardware VLSI Projects, Hardware Quadcopter Projects, MATLAB Projects and Simulation Projects. For MTech final year students we have high quality IEEE projects.

Top Mtech Final year Projects

1) Accelerometer based accident detection System

An accident is a deviation from expected behavior of event that adversely affects the property, living body or persons and the environment. Security in vehicle to vehicle communication or travelling is primary concern for everyone. The work presented in this article documents the designing of an accident detection system. The accident detection system design informs the police control room or any other emergency calling system about the accident.

An accelerometer sensor has been used to detect abrupt change in g-forces in the vehicle due to accident. When the range of g- forces comes under the accident severity, then the microcontroller activates the GSM modem to send pre-stored SMS to a predefined phone number. Also a buzzer is switched on. The product design was tested in various conditions. The test result confirms the stability and reliability of the system.

2) Advanced Traffic Management System/ Automatic Number Plate Reader (ANPR) cameras

ATMS involved a trial run of the fully automated Traffic Regulatory Management System (TRMS), Involving usage of surveillance cameras in the city of Chennai. This project involved installing sophisticated cameras, wireless towers and poles, under the Rs. 3-crore-State government funded project. Automatic Number Plate Reader (ANPR) cameras were installed in 28 out of 42 vantage points in the city, while „Pan Tilt Zoom‟ (PTZ) cameras were deployed in 10 out of 12 busy junctions identified. The traffic police also plan to install 40 CCTV cameras at various junctions.

This is to warn motorists who blatantly violate rules and monitor traffic on arterial roads during peak hours. This integrates various sub-systems (such as CCTV, vehicle detection, communications, variable message systems, etc.) into a coherent single interface that provides real time data on traffic status and predicts traffic conditions for more efficient planning and operations. Dynamic traffic control systems, freeway operations management systems, incident response systems etc. respond in real time to changing conditions.

3) A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER/SUBTRACTOR

This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and subtraction on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP numbers and is based on a fully pipelined circuit. The design presents a novel hardware for pre-signal generation stage and an enhanced version of previously published leading zero stage.

The design can operate at a frequency of 200 MHZ on a Virtex-5 with a latency of 8 cycles. The presented DFP adder/subtractor supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To our knowledge, this is the first hardware FPGA design for adding and subtracting IEEE 754-2008 using decimal64 encoding.

4) An Efficient Implementation of Floating Point Multiplier

In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases.

Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.

5) Reconfigurable FFT using CORDIC based architecture for MIMO-OFDM receivers

Fast Fourier Transform (FFT) is one of the most important algorithm in signal processing and communications and is used in orthogonal frequency division multiplexing (OFDM) systems. FFT are the crucial computational blocks to perform the baseband multicarrier demodulation in a MIMO OFDM system and the hardware complexity will be very high.

This paper proposes a CORDIC based reconfigurable 64 point Fast Fourier Transform which is used for various IEEE standard based WLAN receivers. The CORDIC based FFT block minimizes the hardware complexity because of the elimination of multiplier units and twiddle factors.

This design has the minimal hardware and computational complexity to meet the IEEE standard. In this paper, a reconfigurable FFT has been realized based on CORDIC architecture. The coding for reconfigurable 64 point FFT has been done using VHDL under Xilinx platform. The results are verified and are found to be compatible with Virtex xc6vcx240t-2ff704.

6) Quadcopter Model Q1 and Q2

We one of the best models available and all tested for its working. CITL-TECH Varsity in Bangalore offers the best training and model building workshops to all the hobbyists, engineering students who are interested in developing the modules. now we have released the GPS based quadcopters where it is having the feature of auto return home .A quadcopter, also called a quadrotor helicopter, quadcopter, quadrotors a multi copter that is lifted and propelled by four rotors.

7) Design and control of Segway

The purpose of the project was to design and build a 1/5th scale Segway cart. The cart was modeled after a two wheeled transportation device that uses sophisticated electronics to balance. The cart was designed to follow a line as fast as possible while still keeping a load balanced atop. The cart was limited to several maximums; a height of 6 inches, a mass of 1-kg, wheel diameters between 0.5 and 6 inches, and removable handlebars from 7-9 inches.

The cart also had to support a cylindrical mass with specifications of, a mass up to 2-kg, and a diameter of up to 6-inch. The cart was designed to rock on its wheels over a range of 60 degrees forwards and backwards as well as to follow a black electrical tapeline on a light colored floor. The cart was expected to be self-contained including the power source. With the above design constraints, the cart was then designed to be lightweight, structurally strong enough, inexpensive, and to follow the specified path.

The cart was constructed of hollow aluminum tubing, which made up the frame. The tubing was soldered together. The cart used a spinning hanging mass attached to a potentiometer to sense the angle of tilt. By measuring the change in voltage in the potentiometer as the cart tilted, the balancing of the cart was regulated. Photo sensors were implemented for detecting the black electrical tape and to start the cart in motion.

8) A sleep apnea keeper in a wearable device for Continuous detection and screening during daily life

We intend to design a fully functional breathing monitor for the purpose of detecting events caused by sleep apnea. Sleep apnea is a sleeping disorder characterized by brief interruptions of breathing patterns. This interruption can last a couple seconds, or can be fatal where the patient never regains his or her breath.

We are designing an apparatus that can detect the patients breathing rate, and notify a person monitoring the patient via RF to a handheld monitor. An alarm is sounded at the handheld monitor if the patient’s breathing pattern changes, or halts. We are using pyroelectric sensors (infrared motion detectors) that measure the rate of change of temperature in a given area.

The use of this type of sensor allows us to monitor breathing with absolutely nothing attached to the patient. As well, these sensors are much cheaper then typical breathing monitors available. These features allow us to aim our product at the consumer market where it can be purchased cheaply, and is much less intrusive. Including additional ambient temperature sensors, and a microphone to detect noise, the system can send this information to a portable monitoring device to allow for a fully featured patient monitoring system.

9) Low-Power and Area-Efficient Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA.

Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay.

This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

10) Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection

This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations.

A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.

11) FPGA Design of a Fast 32-bit Floating Point Multiplier Unit

An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant. The implementation of the multiplier module has been done in a top down approach. The sub-modules have been written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E.

12) Design & Implementation of Floating point ALU

In this paper, the implementation of DSP modules such as a floating point ALU are presented and designed. The design is based on high performance FPGA "Cyclone TI" and implementation is done after functional and timing simulation. The simulation tool used is ModelSim. The tool for synthesis and implementation is Quartusn. The experimental results shows the functional and timing analysis for all the DSP modules carried out using high performance synthesis software from Altera.

13) FPGA Implementation of a chaotic oscillator using RK4 method

The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices. For digital realizations the Ordinary Differential Equations (ODE’s) are replaced by a discrete time system. Furthermore numerical values are expressed in a numerical representation.

It is well known that these two discretization processes may strongly affect the chaotic behavior of the system. In previous contributions we considered the use of the Euler’s algorithm in two different numerical representations: (a) integer arithmetics and (b) single floating point IEEE-754 standard. For applications that require a good agreement between the analog chaotic system and its digital counterpart, more involved algorithms and/or numerical representations must be used.

Guided by numerical simulations, in this paper we propose an improvement replacing the Euler’s algorithm by the fourth order Runge Kutta algorithm (RK4). In order to diminish the required hardware a method based on blocks’ reusing is proposed. The procedure is exemplified on a Lorenz CS. The whole design was implemented onto a FPGA, using only 12 % of its logic elements, 13% of its embedded multipliers and 34% of its memory bits.