Arithmetic Core And Digital Electronics

Arithmetic Core And Digital Electronics

IEEE Arithmetic Core And Digital Electronics projects for M.Tech, B.Tech, BE, MS, MCA, BCA Students. CITL Tech Varsity, Bangalore Offers Project Training in IEEE 2018 / 2017 / 2016 Arithmetic Core And Digital Electronics.

  1. Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier
  2. VLSI Design of High Speed Vedic Multiplier for FPGA Implementation
  3. ASIC Design of Signed and Unsigned Multipliers Using Compressors
  4. Area Efficient Modified Vedic Multiplier
  5. Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
  6. Low Power Wallace Tree Multiplier Using Modified Full Adder
  7. An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm.
  8. An Efficient Implementation of Floating Point Multiplier
  9. A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER/SUBTRACTOR
  10. High Speed 16-bit Digital Vedic Multiplier using FPGA
  11. Design and implementation of fast floating point multiplier unit
  12. FPGA Implementation of Vedic Floating Point Multiplier
  13. An Efficient Baugh-Wooley Architecture for Signed & Unsigned Fast Multiplication
  14. An Optimized Design of Reversible Quantum Comparator
  15. Implementation of Open Core Protocol transaction Verification IP using System Verilog UVM methodology
  16. Design and Implementation of CORDIC Processor for Complex DPLL
  17. FPGA Implementation of a chaotic oscillator using RK4 method
  18. Low-Power and Area-Efficient Carry Select Adder
  19. Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
  20. Design and implementation of demodulation technique with complex dpll using cordic algorithm
  21. A New Approach for High Performance and Efficient Design of CORDIC Processor
  22. Design of Plural-Multiplier Based on CORDIC Algorithm for FFT Application
  23. Hardware Efficient Architecture for Generating Sine/Cosine Waves
  24. FPGA Design of a Fast 32-bit Floating Point Multiplier Unit
  25. Design & Implementation of Floating point ALU
  26. FPGA Implementation of Sine and Cosine Value Generators using Cordic Algorithm for Satellite Attitude Determination and Calculators
  27. Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems