Design and Stability Analysis of CNTFET based SRAM Cell
Static Random Access Memory (SRAM) is one of the most crucial and critical memory devices used in today's technological environment. The continuous scaling of CMOS technology significantly limits the performance of 6T SRAM cell in terms of leakage power and stability. With remote chances to further improve the MOSFET technology in future, Carbon Nanotube Field Effect Transistors (CNTFETs) are being widely studied as the possible alternatives. In this paper, the conventional 6T SRAM cell is compared with CNTFET based SRAM cell. The conventional 6T SRAM cell is designed using Cadence Virtuoso Tool in 180nm and 45nm Technology. The Verilog-A code of CNTFET for replacing nMOS and pMOS are separately simulated in Cadence Virtuoso Tool. The CNTFET based SRAM cell is technology independent. The performances are evaluated in terms of leakage power, delay and stability to show that the CNTFET based SRAM cell can successfully replace the CMOS based SRAM cell.