An Efficient Hardware Implementation of Canny Edge Detection Algorithm

The edge detection is one of the key techniques in most image processing applications. The canny edge detection is proven to be able to significantly outperform existing edge detection techniques due to its superior performance. Unfortunately, the implementation of the systems in real-time is computationally complex, high hardware cost with increased latency. The proposed canny edge detection algorithm usesapproximation methods to replace the complex operations; the pipelining is employed to reduce the latency. Finally, this algorithm is implemented on Xilinx Virtex-5 FPGA. When compared with the previous hardware architecture for canny edge detection, the proposed architecture requires fewer hardware costs and takes 1ms to detect the edges of 512x512 image.