An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA
A high performance substitution box (S-Box) FPGA implementation using Galois Field GF (28) is presented in this paper. An optimum number of pipeline registers based on Spartan-3E FPGA is addressed in this paper. The design is fully synthesizable using Verilog and can easily be converted to ASIC implementation. As a result, a fast and area efficient implementation of pipelined S-Box was synthesized and implemented using Xilinx ISE v13.4 and Xilinx Spartan-3E XC3S2500E-4 FPGA as the target device. Hardware testing was performed and the results were verified and found to be identical to simulation results. The appropriate number of pipeline stages is found to be two stages in terms of LUTs needed and speed. The timing results from the ‘Place and Route’ report indicate that the maximum clock frequency which can be applied to the design is 701.262MHz, with an output delay that is equal to 2 clock cycles.