Electrocardiogram (ECG) is the most important and widely used method to study the heart related diseases. The detailed study of ECG graph by the medical practitioner helps him to understand and identify the condition of the heart. Based on the information retrieved from the ECG graph the patient can be given proper treatment.
The person having a medical history of heart ailments will have to maintain a record of all the ECG papers for timely analysis and diagnosis of the diseases. This process requires large storage space and extensive manual effort.The conventional technique of visual analysis to inspect the ECG signals by doctors or physicians are not effective and time consuming. Therefore, an automatic system which involves digital signal integration and analysis is required.
In this study a MATLAB-based tool is being designed to convert electrocardiography (ECG) information from paper charts into digital ECG signals. Here we develop a method that involves processing of ECG paper records by an efficient and iterative set of digital image processing techniques for the conversion of ECG paper image data to time series digitized signal form, resulting in convenient storage and retrieval of ECG information. In addition, this tool can be used to potentially integrate digitized ECG information with digital ECG analysis programs and with the patient's electronic medical record.
This paper proposes multilevel topologies based on the concept of nested arrangement. Such topologies are called nested multilevel converters, since the central point of the legs are connected at the same point, with the external legs involving the internal ones. Nested configurations present advantages as compared to the equivalent NPC topologies in terms of reduced number of diodes and consequently higher efficiency.
In addition to proposing a new family of power electronics converters, this paper presents an optimized pulse widthmodulation strategy that allows synthesizing voltage waveforms with higher quality, a losses comparison with the NPC topology, and a general comparison with other topologies proposed in the technical literature. Simulated and experimental results are presented to validate the theoretical expectations.
A new auxiliary circuit for an ac–dc single-stage power-factor-corrected (SSPFC) full-bridge-type converter is proposed in this paper. The new auxiliary circuit is simple, handles low power, and is active only when the converter is operating under light load conditions. In this paper, the operation of an SSPFC converter is briefly reviewed and the main principle behind the auxiliary circuit is explained. The new auxiliary circuit is introduced, its operation is explained, and its feasibility in a multilevel SSPFC is confirmed with experimental results.
Two stage AC-DC converters consisting of frontend Power Factor Correction (PFC) AC-DC boost converter followed by an isolated DC-DC converter are the industry workhorse for powering network servers, telecom and other DC loads. Such converters are powered from single-phase ac utility mains. For proper operation of these loads the AC-DC converterprovides a regulated DC voltage that ranges from 12V to 48V depending on the type of load.
For safe uninterrupted operation during sudden intermittences in power supplied from the AC mains, the AC-DC power converter should be able to supply such loads with constant DC output voltage in order to prevent them from unwanted resetting. The maximum duration for which the AC-DC converter can supply the load with regulated DC output voltage at its maximum output power after input AC mains failure, is known as “hold-up-time (HUT)” of the converter. This paper proposes a novel DC-DC non-resonant full-bridge converter with extended hold-up-time capability with reduced input storage capacitance.
This paper presents a matrix based isolated three phase AC-DC converter suitable for aircraft application. A three -phase to single-phase (3x1) matrix topology with novel modulation scheme named as Switched Rectifier Inverter (SRI) is introduced for direct line frequency AC to high frequency AC conversion which in effect, eliminates the requirement of bulky DC link capacitor and therefore, provides high power density essential for the aircraft systems.
The high frequency AC output of the matrix (3x1) converter is processed by high frequency transformer followed by rectifier to obtain isolated DC output voltage. The operation of the proposed converter with SRI modulation scheme is explained. Moreover, the input power quality under the proposed modulation scheme is discussed for wide load range. Comprehensive simulation is carried out in PSIM for an example converter of input 120 V (rms), 400 Hz AC to 400 V DC with 8 kW power.
The three-phase three-level diode clamped inverter due to its supreme performance compared to a two-level inverter is one of the widely used multilevel inverter topology for medium voltage, high power applications. One of the popular control strategies for the inverter is space vector pulse width modulations (SVPWM) which has superior advantages in terms of its implementation and harmonic reduction.
A three-level neutral point clamped (NPC) inverter with space vector modulation is presented in this paper. Duty cycles of the inverter switches are calculated based on a two-level inverter space vector diagram. A switching sequence is proposed in this paper to reduce the total harmonic distortion (THD) in the line current as well as to increase the C bus utilization of the inverter.
The current harmonics of conventional SVPMW based inverter is compared for various modulation indices with the new modulation method and the result is encouraging.
The Soft Switching Three Level Inverter – abbreviated to S3L Inverter – was first introduced in 2011. It is a novel circuit topology for PWM inverters, whose areas of application include electrical drives and grid-tie inverters for photovoltaic installations and wind power plants, and for power supplies. It is of very simple design and therefore inexpensive. It is implemented completely as soft switching and hence offers very low switching losses.
This means that its efficiency is very high, and it can achieve very high values for the switching frequency. This paper begins by describing how the device functions. It then goes on to discuss specialised methods of control. A variant of the S3L Inverter with a deactivatable snubber circuit is presented. A quantitative comparison between a well-known hard switching NPC 3-level inverter and the novel S3L Inverter using 90 kVA (three-phase) prototypes illustrates the advantages of the S3L inverter.
Though CMOS logic inverter is widely appreciated because of its negligible static power consumption still sometimes it is deprecated because of the high dynamic power consumption. The high dynamic power consumption is because of the charging and discharging of the load capacitor and also because of the unwanted short-circuits current from Vdd to ground. The proposed three transistor saturated NMOS inverter reduces the short-circuit current and hence reduces the overall power consumption.
The proposed inverter reduces the average power consumption by 35% for any input signal of frequency less than or equal to 1 MHz and by 15% for any input signal up to around 10MHz. But the power consumption slowly increases when the input frequency goes beyond 100 MHz. So the proposed inverter can be used in MHz applications to save a good amount of power.
Solar energy is one of the renewable energy which is used to generate electricity with the help of PV arrays. DC-DC converter is used to step up the DC voltage from PV arrays and then it is connected to an inverter for AC applications. Conventional inverters have many issues like non sinusoidal output, high total harmonic distortion (THD), high switching stress and more number of switches. So multilevel inverter (MLI) have gained much importance over conventional inverters for high voltage and high power applications, due to the increased number of voltage levels producing less number of harmonics.
In this paper, a cascaded asymmetric multilevel inverter is proposed which contains minimum number of switches and can be employed in AC applications using solar energy. The proposed topology consists of 25 output levels using 10 switches with near sinusoidal output, thereby reducing gate driver circuitry and optimizing circuit layout.
Asymmetric multilevel inverter is more advantageous than symmetric multilevel inverter in obtaining more number of output levels using same number of voltage sources. The other advantages of proposed topology are low voltage stress and reduced THD. The THD for proposed inverter circuit is only 4.98%. Modeling and simulation is carried out using MA TLAB/SIMULINK.
This article introduces the design of a three-switch single-phase single-stage grid-connected buck-boost photovoltaic inverter topology for residential applications. The proposed design topology has numerous desirable features such as better utilization of the photovoltaic array, low cost, compact size, simpler control and higher efficiency.
For switching of inverter power circuit, we used a combination of sinusoidal pulse width modulation (SPWM) and square wave signal under grid synchronization condition. Moreover, to control SPWM duty cycle and to regulate the inverter's instantaneous ac output current, a closed-loop SPWM control scheme is employed to stabilize the output as fast as possible. The design and analysis of the inverter control circuit and grid synchronization methods are portrayed in detail. T
he proposed design is mathematically modeled which is simulated in PSIM. Finally, the simulation results are presented to verify the viability of the proposed single stage three-switch buck-boost inverter for grid-connected photovoltaic application and confirmed the capability of the inverter to feed a sinusoidal current to the utility grid at a wide range of input photovoltaic dc voltage.
In conventional inverters, implementation of a transformer greatly enhances the Total Harmonic Distortion
(THD) which is counted to have a negative impact on the inverter output. In order to overcome this limitation, transformer can be replaced by buck and boost converters thereby making a transformer-less inverter which will greatly reduce the THD and enhance the efficiency. In this paper, the design of a single stage buck and boost converters has been presented for photovoltaic inverter applications.
The proposed design employs a single-stage switch mode buck converter and a single-stage switch mode boost converter. The converters are so designed that the boost converter provides an output voltage of 312V DC from 24V PV array while the buck converter provides an output voltage of 7.07V pulsated DC from 312V AC grid. The designed buck and boost converters are then employed to run a single-phase full bridge inverter. The circuit is simulated using the PSIM software. The simulation results show that the designed buck and boost converters can be used to replace transformers from conventional inverter circuit to make low-THD, highly efficient and cost effective transformer-less inverter topology.
In this paper, an integrated three-port bidirectional dc–dc converter for a dc distribution system is presented. One port of the low-voltage side of the proposed converter is chosen as a current source port which fits for photovoltaic (PV) panels with wide voltage variation. In addition, the interleaved structure of the current source port can provide the desired small current ripple to benefit the PV panel to achieve the maximum power point tracking (MPPT).
Another port of the low-voltage side is chosen as a voltage source port interfaced with battery that has small voltage variation; therefore, the PV panel and energy storage element can be integrated by using one converter topology. The voltage port on the high-voltage side will be connected to the dc distribution bus. A high-frequency transformer of the proposed converter not only provides galvanic isolation between energy sources and high voltage dc bus, but also helps to remove the leakage current resulted from PV panels. The MPPT and power flow regulations are realized by duty cycle control and phase-shift angle control, respectively.
Different from the single-phase dual-half-bridge converter, the power flow between the low-voltage side and high-voltage side is only related to the phase-shift angle in a large operation area. The system operation modes under different conditions are analyzed and the zero-voltage switching can be guaranteed in the PV application even when the dc-link voltage varies. Finally, system simulation and experimental results on a 3-kW hardware prototype are presented to verify the proposed technology.
A single-stage ac–dc power electronic converter is proposed to efficiently manage the energy harvested from electromagnetic microscale and mesoscale generators with low-voltage outputs. The proposed topology combines a boost converter and a buck-boost converter to condition the positive and negative half portions of the input ac voltage, respectively.
Only one inductor and capacitor are used in both circuitries to reduce the size of the converter. A 2 cm × 2 cm, 3.34-g prototype has been designed and tested at 50-kHz switching frequency, which demonstrate 71% efficiency at 54.5 mW. The input ac voltage with 0.4-V amplitude is rectified and stepped up to 3.3-V dc.
Detailed design guidelines are provided with the purpose of minimizing the size, weight, and power losses. The theoretical analyses are validated by the experiment results.
This paper proposed an improved phase disposition pulse width modulation (PDPWM) for a modular multilevel inverter which is used for Photovoltaic grid connection. This new modulation method is based on selective virtual loop mapping, to achieve dynamic capacitor voltage balance without the help of an extra compensation signal. The concept of virtual submodule (VSM) is first established, and by changing the loop mapping relationships between the VSMs and the real submodules, the voltages of the upper/lower arm’s capacitors can be well balanced.
This method does not requiring sorting voltages from highest to lowest, and just identifies the MIN and MAX capacitor voltage’s index which makes it suitable for a modular multilevel converter with a large number of submodules in one arm. Compared to carrier phase-shifted PWM (CPSPWM), this method is more easily to be realized in field- programmable gate array and has much stronger dynamic regulation ability, and is conducive to the control of circulating current. Its feasibility and validity have been verified by simulations and experiments.