In design of Finite Impulse Response (FIR) filter using adder, coefficients and multiplication are used. Multiple Constant Multiplication (MCM) is the algorithm which is used in FIR designing to minimize complexity of the circuit, increased delay and multiplication using large area. These problems can be optimized by using new technique known as digit-serial multiple constant multiplications.
It reduces the complexity, delay and area utilization. Along with this already existed method, the modified carry select adder implemented in the current paper. It shows that there should be 10-20% increment in power efficiency and 50% reduction in delay compared to already exist techniques. Index Terms— CSA; Delay; FIR filter; GB; MCM; VLSI.
This paper focused on the design of 32 bit IEEE 754 single precision floating point architecture for 8 point FFT. The total design is in combinational form. The FFT design is simulated in Active HDL. Results are verified with MATLAB simulation. Correctness is obtained up to twenty two bit.
The design is tested for complex input data (separately for real and imaginary data). For low power design pipelining is used i.e. forward path cutset to FFT stages. Using two stages pipelining, the power of architecture is calculated in Design Vision tool of Synopsys by 45nm technology file. By this scheme, the total power required is reduce up to 35%
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This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations.
A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.
In recent years FPGA systems are replacing dedicated Programmable Digital Signal Processor (PDSP) systems due to their greater flexibility and higher bandwidth, resulting from their parallel architecture. This paper presents the applicability of a FPGA system for speech processing. Here adaptive filtering technique is used for noise cancellation in speech signal. Least Mean Squares (LMS ) ,
one of the widely used algorithm in many signal processing environment , is implemented for adaption of the filter coefficients. The cancellation system is implemented in VHDL and tested for noise cancellation in speech signal. The simulation of VHDL design of adaptive filter is performed and analyzed on the basis of Signal to Noise ratio (SNR) and Mean Square Error (MSE).
Dynamic Electrocardiograph (ECG) monitoring (known as Holter) plays an important role in the earlier detection and diagnosis of various cardiovascular diseases. ECG signals obtained from Holter systems normally contain a lot of noises and artifacts. These noises degrade signal quality, which may be critical for routine monitoring and diagnosis.
To solve the problem, a reconfigurable overlapping fast Fourier transform/ inverse fast Fourier transform (FFT/IFFT) filter for suppressing the power-line interference and the high-frequency noise is presented in this paper. The filter is based on a 12-lead Holter system with a high-performance analogue front-end and a field-programmable gate array (FPGA) for enhanced digital processing.
This paper analyzes the performance of the reconfigurable overlapping FFT/IFFT filter in ECG de-noising applications and validate it by real-world emulations. Furthermore, the de-noising performance of the reconfigurable overlapping FFT filter was evaluated.
A small, fine-grained systolic FFT architecture is described that is fast, programmable, can do non-power-of-two DFTs, and provides a higher signal-to-noise ratio for a given fixed-point word length than traditional block floating point approaches. To demonstrate the basic architecture, several designs were implemented using 65nm FPGA technology:
(1) fixed-size 256-point and 1024-point circuits;
(2) a power-of-two variable FFT circuit for LTE OFDM; and
(3) a non-power-of-two circuit for LTE SC-FDMA DFT computations,
That is programmed by entering parameter values into a single ROM memory. These three circuits demonstrate >37%, 62% and >100% higher throughputs than the other pipelined and memory-based FFTs to which they are compared. These circuits run at clocks speeds as high as 566 MHz, 46% higher than any other circuit in the comparisons. Finally, the architecture provides scalable throughput by increasing the array size.
This paper proposes partial reconfigurable FIR filter design using systolic Distributed Arithmetic (DA) architecture optimized for FPGAs. To implement computationally efficient, low power, high speed Finite Impulse Response (FIR) filter a two dimensional fully pipelined structure is used. To reduce the partial reconfiguration time a new architecture for the Look-Up Table (LUT) in distributed arithmetic is proposed.
The FIR filter is dynamically reconfigured to realize low pass and high pass filter characteristics by changing the filter coefficients in the partial reconfiguration module. The design is implemented using XUP Virtex 5 LX110T FPGA kit. The FIR filter design shows improvement in configuration time and efficiency.
This work presents the combining of two methods, which are discrete Fourier transform spread (DFT-spread) and 2×2 space time block codes (STBC), to improve the system performance for polarization division multiplexing (PDM) coherent optical orthogonal frequency division multiplexing (CO-OFDM) communication systems. The system performances are generally measured by the unit of bit error rate (BER). For 64-QAM, the communication length of 850 km can be achieved at the forward error control (FEC) limit.
Digital filters are widely used in signal processing and communication systems. In some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that exploit the filters’ structure and properties to achieve fault tolerance have been proposed. As technology scales, it enables more complex systems that incorporate many filters. In those complex systems,
it is common that some of the filters operate in parallel, for example, by applying the same filter to different input signals. Recently, a simple technique that exploits the presence of parallel filters to achieve fault tolerance has been presented. In this brief, that idea is generalized to show that parallel filters can be protected using error correction codes (ECCs) in which each filter is the equivalent of a bit in a traditional ECC.
This new scheme allows more efficient protection when the number of parallel filters is large. The technique is evaluated using a case study of parallel finite impulse response filters showing the effectiveness in terms of protection and implementation cost.
This paper describes the architecture and operating principles of two digital pulse-width modulator (DPWM) implementations for low-cost field-programmable gate arrays (FPGAs). Both architectures are based on a counter comparator block to process the most significant bits (MSB) portion of the reference input, enriched with additional elements to enhance duty-cycle resolution according to the less significant bits (LSB).
The first architecture described has already been reported in the literature, it uses the on-chip PLL blocks to generate fixed delays and a selector to choose the one corresponding with the desired duty-cycle. Post-fitting adjustments of PLL delays are required to compensate delay differences between the diverse signal paths across the selector.
In the second architecture described, a serializer-deserializer (SERDES) module is used to serialize a thermometer-coded representation of the LSB portion of the input. This serialization technique is commonly used for data transmission on high-speed serial I/O data transmission standards like LVDS and is extensively supported by FPGA providers. Experimental results are presented for both architectures synthesized on standard low-cost FPGA chips, showing very good linearity and resolutions up to 1ns. The first architecture provides a moderately better resolution. The second architecture, on the other hand, is a much more robust solution as it requires no post fitting delay adjustments.
In process to create a more suitable and accurate pulse processing system FPGA system is developed. Analog system takes wide space for pulse processing. FPGA technology has replaced this disadvantage. It has become an extremely cost-effective means of off- loading computationally intensive digital signal processing algorithms to improve overall system performance.
The digital filter implementation in FPGA, utilizing the dedicated hardware resources can effectively achieve application-specific integrated circuit (ASIC)-like performance while reducing development time cost and risks. A low-pass filter can be implementing on FPGA. MATLAB tool with FPGA system is best way to design digital system.
Digital frequency input and output (typically in the range 1 Hz to 100 kHz) for data transmission are employed in many industrial applications. This paper provides the following elaborations of the ISIE’07 conference paper. A thorough literature review suggests that previous techniques can be classified into three basic approaches.
Theoretical expressions for the errors of each are derived and compared with the new approach developed by the authors. Each method has been implemented in a more recent field programmable gate array architecture (Spartan 3), and the results are consistent with the theoretical values. The new method provides a precision of 6 × 10−6% or better for all frequencies, based on a 40-MHz clock.
In this paper, we present a low latency systolic Montgomery multiplier over based on irreducible polynomials. An efficient algorithm is presented to decompose the multiplication into a number of independent units to facilitate parallel processing. Besides, a novel so-called “pre-computed addition” technique is introduced to further reduce the latency.
The proposed design involves significantly less area-delay and power-delay complexities compared with the best of the existing designs. It has the same or shorter critical-path and involves nearly one-fourth of the latency of the other in case of the National Institute of Standards and Technology recommended irreducible polynomials.
Implementation of Adaptive FIR Filter for Pulse Doppler Radar
Digital Signal Processing (DSP) systems involve a wide spectrum of DSP algorithms and their realizations are often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. This paper presents the design of Adaptive Finite Impulse Response (FIR) filter for moving target detection in various clutter conditions in Radar Receiver.
The design uses pipelined Coordinate Rotation Digital Computer (CORDIC) unit and pipelined multiplier to get high system throughput and reduced latency in each of the pipelined stage. Saving area on silicon substrate is essential to the design of any pipelined CORDIC. The area reduction in proposed design can be achieved through optimization in the number of micro rotations. For better adaptation and performance of Adaptive Filters and to minimize quantization error, the numbers of iterations are also optimized.
Aiming at the requirements of real time signal processing, a cut-off frequency of 100 KHz, 16-tap direct form FIR linear-phase low-pass filter using Kaiser Window function was designed out based on DSP Builder system modeling approach. The signal waveforms in time domain and frequency domain before and after filtering were analyzed. Ultimately, a highest response frequency of 61.71MHz high-speed FIR low-pass filter was implemented on EP2C35F672C8 FPGA. Design efficiency and filter
performance has been greatly improved.
The adaptive filter constitutes an important part of the statistical signal processing. Whenever there is a requirement to process signals that result from operation in an environment of unknown statistics, the use of an adaptive filter offers an attractive solution to the problem as it usually provides a significant improvement in performance over the use of a fixed filter designed by conventional methods.
Furthermore, the use of adaptive filters provides new signal-processing capabilities that would not be possible otherwise. We thus find that adaptive filters are successfully applied in such diverse fields as communications, control, radar, sonar, seismology, and biomedical engineering.