1.The Alleviation of Low Power Schmitt Trigger Using FinFET Technology
In this paper, we designed Schmitt trigger using CMOS low power design technique at 45nm technology. With the advancement of technology, different parameters have been calculated and analyzed to determine the performance of the circuit. With the change in technology, the aspect ratio of transistor sizing,
variation in parameters also takes place. Different techniques are applied for the reduction in power consumption at the trade off with delay and area. In this paper we use novel FinFET technique to decrease the leakage power in the circuit. Schmitt trigger is a positive feedback amplifier that converts any continuous time varying signal to pulse wave. It forms the comparator of modern analog to digital convertor circuits, and it provides good noise immunity, thus it is used in communication.
Parameters like slew rate, propagation delay, energy delay product etc of the circuit are calculated in both CMOS and FinFET technique and compared. Leakage power obtained using FinFET is 12.08PW which is very less to that of bulk CMOS. Designing is done with variable voltage supply and the performance of the circuit is observed at different points. The circuit is simulated in Cadence virtuoso tool version 6.1 output of all is compared.
2.FinFET Based 4-BIT Input XOR/XNOR Logic Circuit
In this paper a structure for direct 4-BIT XOR/XNOR logic cell is proposed. This structure is proposed using pass transistor logic with FinFETs. This structure has less delay for the reason that its critical path consists of a minimum number of transistors. The basic advantage of this circuit is their symmetry in the logic. This design has a full voltage swing at the outputs and hence it has the good driving capability. The
proposed design produces perfect outputs, even at low voltages and at high frequencies with the lesser transistor count. The proposed design is simulated using Cadence 20 nm FinFET technology at various supply voltages assorting from +0.6 V to +0.9 V. The simulation results illustrate that the proposed design has less delay and as well as less power consumption.
3.Design Considerations for Pipelined ADCs
Design considerations for pipelined analog-todigital converters (ADCs) are discussed. The main requirements for DC gain and unity-gain frequency, reference voltage stability and capacitor mismatch versus desired SFDR of pipelined ADCs are presented. Examples of voltage reference circuits and a clock distribution circuit as well as Cadence Virtuoso and MATLAB simulation results are provided.
4.Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
In this paper, we introduce an architecture of pre-encoded multipliers for digital signal processing applications based on off-line encoding of coefficients. To this extend, the Non-Redundant radix-4 Signed-Digit (NR4SD) encoding technique, which uses the digit values f_1; 0;þ1;þ2g or f_2;_1; 0;þ1g, is proposed leading to a multiplier design with less complex partial products implementation. Extensive experimental analysis verifies that the proposed pre-encoded NR4SDmultipliers, including the coefficients memory, are more area and power efficient than the conventional Modified Booth scheme.
5.Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. The proposed multiplier receives and outputs the data with binary representation and uses only one-level carry-save adder (CSA) to avoid the carry propagation at each addition operation.
This CSA is also used to perform operand pre computation and format conversion from the carry save format to the binary representation, leading to a low hardware cost and short critical path delay at the expense of extra clock cycles for completing one modular multiplication. To overcome the weakness, a configurable CSA (CCSA), which could be one full-adder or two serial half-adders, is proposed to reduce the extra clock cycles for operand pre computation and format conversion by half.
In addition, a mechanism that can detect and skip the unnecessary carry-save addition operations in the one-level CCSA architecture while maintaining the short critical path delay is developed. As a result, the extra clock cycles for operand pre computation and format conversion can be hidden and high throughput can be obtained. Experimental results show that the proposed Montgomery modular multiplier can achieve higher performance and significant area–time product improvement when compared with previous designs.
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