Top MS Final year Projects List
1.Reconfigurable FFT using CORDIC based architecture for MIMO-OFDM receivers
Fast Fourier Transform (FFT) is one of the most important algorithm in signal processing and communications and is used in orthogonal frequency division multiplexing (OFDM) systems. FFT are the crucial computational blocks to perform the baseband multicarrier demodulation in a MIMO OFDM system and the hardware complexity will be very high.
This paper proposes a CORDIC based reconfigurable 64 point Fast Fourier Transform which is used for various IEEE standard based WLAN receivers. The CORDIC based FFT block minimizes the hardware complexity because of the elimination of multiplier units and twiddle factors. This design has the minimal hardware and computational complexity to meet the IEEE standard. In this paper, a reconfigurable FFT has been realized based on CORDIC architecture. The coding for reconfigurable 64 point FFT has been done using VHDL under Xilinx platform. The results are verified and are found to be compatible with Virtex xc6vcx240t-2ff704.
2.MCC-OSGi: An OSGi-based mobile cloud service model
3.Implementation OF Real Time Passenger Information System Using GPRS (RTPIS)
RTPIS provides travel information to passengers and tourists enabling them to make informed decisions about modes, routes and departure times. The RTPIS framework can be broadly divided into two contexts: (1)Pre-trip context and (2) On-trip context. Pre-trip context:-The former provides information like timings, fares and routes well before the commencement of travel, through the Internet or the Short Messaging Service (SMS). The Ontrip context: - provides information like location and places of interest (POI) while on the move. This is achieved using on-board and at-stop terminals (displays and audio announcement units).
4.Advanced Rural Transportation Systems (ARTS)
Advanced Rural Transportation Systems (ARTS) provide information about remote road and other transportation systems. Examples include automated road and weather conditions reporting and directional information. This type of information is valuable to motorists travelling to remote or rural areas. This has been widely implemented in the United States and will be a valuable asset to countries like India, where rural areas are widely distributed
5.Advanced Traffic Management System/ Automatic Number Plate Reader (ANPR) cameras
ATMS involved a trial run of the fully automated Traffic Regulatory Management System (TRMS), Involving usage of surveillance cameras in the city of Chennai. This project involved installing sophisticated cameras, wireless towers and poles, under the Rs. 3-crore-State government funded project. Automatic Number Plate Reader (ANPR) cameras were installed in 28 out of 42 vantage points in the city, while „Pan Tilt Zoom‟ (PTZ) cameras were deployed in 10 out of 12 busy junctions identified.
The traffic police also plan to install 40 CCTV cameras at various junctions. This is to warn motorists who blatantly violate rules and monitor traffic on arterial roads during peak hours. This integrates various sub-systems (such as CCTV, vehicle detection, communications, variable message systems, etc.) into a coherent single interface that provides real time data on traffic status and predicts traffic conditions for more efficient planning and operations. Dynamic traffic control systems, freeway operations management systems, incident response systems etc. respond in real time to changing conditions.
6.Advanced Public Transportation System APTS/ Intelligent Transport System
One application implemented in APTS area is GPS vehicle tracking system in public transport buses (Bangalore, Chennai, Indore) to monitor vehicle routing and frequency .so that passengers do not have to wait long hours for a bus.
The objective is to provide Global Positioning System based passenger information system to help passengers utilize their waiting time at bus stops more efficiently as well as to reduce the uncertainty and associated frustrations. Display boards with high quality light emitting diode in wide-view angle are provided at bus stops so that passengers can read the information.
It displays the number and destination of the approaching bus, expected time of arrival, and messages of public interest. Even SMS Alert is provided to the Ticket reserved passengers from Main server Applies state-of-art transportation management and information technologies to public transit systems to enhance efficiency of operation and improve safety. It includes real-time passenger information systems, automatic vehicle location systems, bus arrival notification systems, and systems providing priority of passage to buses at signalized intersections (transit signal priority).
7.Microcontroller based anesthesia machine
In the hospitals when any major operation is performed, the patient must be in anesthetize condition. If the operation lasts for a long time, say for suppose for 5 or 7 hours, complete dose of anesthesia cannot be administered in a single stroke. It may lead to the patient’s death. If lower amount of anesthesia is administered, the patient may get up in midst to avoid this, the anesthetist administers few milliliters of anesthesia per hour to the patient. If the anesthetist fails to administer the anesthesia to the patient at the particular time interval, other Allied problems may arise.
To overcome such hazardous problems the design of an automatic operation of an anesthesia machine based on a micro-controller is effective. In this system provided syringe infusion pump along with the microcontroller . The anesthetist can set the level of anesthesia in terms of milliliters per hour to administer anesthesia to the patient. After receiving the signal from the temperature sensor heart beat sensor and respiration sensor , the microcontroller controls the signal to the desire level and fed into the stepper motor to drive the infusion pump in proper manner.
The anesthesia is administered to the patient according to the stepper motor rotation.This particular paper will be very much useful to physicians to see the current position of anesthesia of the patients. If the level of anesthesia is decreased to lower level (set value), the alarm will be initiated to alert the physician to refill the anesthesia in the Syringe Pump to continue the process
8.Quadcopter Model Q2
9.Quadcopter Model Q1
10.Design and control of Segway
The purpose of the project was to design and build a 1/5th scale Segway cart. The cart was modeled after a two wheeled transportation device that uses sophisticated electronics to balance. The cart was designed to follow a line as fast as possible while still keeping a load balanced atop.
The cart was limited to several maximums; a height of 6 inches, a mass of 1-kg, wheel diameters between 0.5 and 6 inches, and removable handlebars from 7-9 inches. The cart also had to support a cylindrical mass with specifications of, a mass up to 2-kg, and a diameter of up to 6-inch. The cart was designed to rock on its wheels over a range of 60 degrees forwards and backwards as well as to follow a black electrical tapeline on a light colored floor.
The cart was expected to be self-contained including the power source. With the above design constraints, the cart was then designed to be lightweight, structurally strong enough, inexpensive, and to follow the specified path. The cart was constructed of hollow aluminum tubing, which made up the frame. The tubing was soldered together.
The cart used a spinning hanging mass attached to a potentiometer to sense the angle of tilt. By measuring the change in voltage in the potentiometer as the cart tilted, the balancing of the cart was regulated. Photo sensors were implemented for detecting the black electrical tape and to start the cart in motion
11.A sleep apnea keeper in a wearable device for Continuous detection and screening during daily life
We intend to design a fully functional breathing monitor for the purpose of detecting events caused by sleep apnea. Sleep apnea is a sleeping disorder characterized by brief interruptions of breathing patterns. This interruption can last a couple seconds, or can be fatal where the patient never regains his or her breath. We are designing an apparatus that can detect the patients breathing rate, and notify a person monitoring the patient via RF to a handheld monitor.
An alarm is sounded at the handheld monitor if the patient’s breathing pattern changes, or halts. We are using pyroelectric sensors (infrared motion detectors) that measure the rate of change of temperature in a given area. The use of this type of sensor allows us to monitor breathing with absolutely nothing attached to the patient.
As well, these sensors are much cheaper then typical breathing monitors available. These features allow us to aim our product at the consumer market where it can be purchased cheaply, and is much less intrusive. Including additional ambient temperature sensors, and a microphone to detect noise,
the system can send this information to a portable monitoring device to allow for a fully featured patient monitoring system.
12.Low-Power and Area-Efficient Carry Select Adder
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture.
The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
13.Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to redefine the elementary angles for reducing the number of CORDIC iterations.
A generalized micro-rotation selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the number of iterations depending on the accuracy, area and latency requirements. Compared to the existing recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device.
14.A New Approach for High Performance and Efficient Design of CORDIC Processor
This paper presents a new approach for the high performance and hardware efficient design of coordinate rotation digital computer (CORDIC) processor structure. The proposed design approach completely eliminates the ROM requirement of constant arctangent values. Furthermore, efficient designs of carry look ahead adders (CLAs), exploiting one input as constant, in the angle adder/subtractor datapath speeds-up the computation while maintaining regularity.
The proposed architecture is implemented in FPGA as well as in 180nm standard cell library. The proposed implementation has about 39% delay improvement in FPGA and about 34% delay improvement in standard cell technology as compared to basic structure. About 47% power savings has been achieved in the proposed structure.
15.FPGA Design of a Fast 32-bit Floating Point Multiplier Unit
An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008 standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay caused by the propagation of the carry by implementing adders having the least power delay constant. The implementation of the multiplier module has been done in a top down approach. The sub-modules have been written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E.
16.Design & Implementation of Floating point ALU
In this paper, the implementation of DSP modules such as a floating point ALU are presented and designed. The design is based on high performance FPGA "Cyclone TI" and implementation is done after functional and timing simulation. The simulation tool used is ModelSim. The tool for synthesis and implementation is Quartusn. The experimental results shows the functional and timing analysis for all the DSP modules carried out using high performance synthesis software from Altera.
17.FPGA Implementation of a chaotic oscillator using RK4 method
The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient to have hardware implementations for both, analog and digital versions. Discrete components, Micro Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible choices.
For digital realizations the Ordinary Differential Equations (ODE’s) are replaced by a discrete time system. Furthermore numerical values are expressed in a numerical representation. It is well known that these two discretization processes may strongly affect the chaotic behavior of the system. In previous contributions we considered the use of the Euler’s algorithm in two different numerical representations: (a) integer arithmetics and (b) single floating point IEEE-754 standard. For applications that require a good agreement between the analog chaotic system and its digital counterpart, more involved algorithms and/or numerical representations must be used.
Guided by numerical simulations, in this paper we propose an improvement replacing the Euler’s algorithm by the fourth order Runge Kutta algorithm (RK4). In order to diminish the required hardware a method based on blocks’ reusing is proposed. The procedure is exemplified on a Lorenz CS. The whole design was implemented onto a FPGA, using only 12 % of its logic elements, 13% of its embedded multipliers and 34% of its memory bits.
